// Copyright (C) 1953-2021 NUDT
// Verilog module name - command_parse_and_encapsulate_pdg
// Version: V4.0.20220525
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module command_parse_and_encapsulate_pdg
(
        i_clk,
        i_rst_n,
        
        iv_pkt_discard_cnt,
        
        iv_addr,                         
        iv_wdata,                        
        i_wr_pdg,         
        i_rd_pdg,         
        
        o_wr_pdg,          
        ov_addr_pdg,       
        ov_rdata_pdg 
);

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;

input       [15:0]      iv_pkt_discard_cnt;

input       [18:0]      iv_addr;                         
input       [31:0]      iv_wdata;                        
input                   i_wr_pdg;         
input                   i_rd_pdg;         

output reg              o_wr_pdg;          
output reg [18:0]       ov_addr_pdg;       
output reg [31:0]       ov_rdata_pdg;
            
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        o_wr_pdg           <= 1'b0;
        ov_addr_pdg        <= 19'b0;
        ov_rdata_pdg       <= 32'b0;
    end
    else begin
        if(i_wr_pdg)begin//write
            o_wr_pdg           <= 1'b0;
            ov_addr_pdg        <= 19'b0;
            ov_rdata_pdg       <= 32'b0;
        end
        else if(i_rd_pdg)begin//read
            if(iv_addr == 19'b0)begin
                o_wr_pdg           <= 1'b1;
                ov_addr_pdg        <= iv_addr;
                ov_rdata_pdg       <= {16'b0,iv_pkt_discard_cnt};
            end
            else begin
                o_wr_pdg           <= 1'b0 ;
                ov_addr_pdg        <= 19'b0;
                ov_rdata_pdg       <= 32'b0;            
            end
        end
        else begin
            o_wr_pdg         <= 1'b0;
            ov_addr_pdg      <= 19'b0;
            ov_rdata_pdg     <= 32'b0;
        end        
    end
end       
endmodule